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| EF6805U3 8-BIT MICROCOMPUTER UNIT .32TTL/ .24BI .8I .3776BYTESOFUSERROM .112BYTESOFRAM .SELF.ZERO.I .5VSI .10POWERFULADDRESSI .BYTE .SI .POWERFUL .FULLSETOFCONDI .MEMORYUSABLEASREGI .COMPLETE SOFTWARE FEATURES HARDWARE FEATURES CMOS COMPATIBLE I/O LINES DIRECTIONAL (8 lines are LED compatible) NPUT-ONLY CHECK MODE CROSSING DETECT/INTERRUPT NTERNAL 8-BIT TIMER WITH 7-BIT SOFTWARE PROGRAMMABLE PRESCALER AND CLOCK SOURCE NGLE SUPPLY DESCRIPTION The EF6805U3 Microcomputer Unit (MCU) is a member of the 6805 Family of low-cost single-chip Microcomputers. The 8-bit microcomputer contains a CPU, on-chip CLOCK, ROM, RAM, I/O, and TIMER. It is designed for the user who needs an economical microcomputer with the proven capabilities of the 6800-based instruction set. A comparison of the key features of several members of the 6805 Family of Microcomputers is shown at the end of this data sheet. The following are some of the hardware and software highlights of the EF6805U3 MCU. NG MODES EFFICIENT INSTRUCTION SET WITH TRUE BIT MANIPULATION, BIT TEST, AND BRANCH INSTRUCTIONS NGLE INSTRUCTION MEMORY EXAMINE/CHANGE INDEXED ADDRESSING FOR TABLES TIONAL BRANCHES STER/FLAGS DEVELOPMENT SYSTEM SUPPORT ON INICE 1 P (PDIP40) FN (PLCC 44) .8 .8BI .CRYSTALORLOW.LOWVOLTAGEI .VECTORED .USER PIN CONNECTIONS USER SELECTABLE OPTIONS BIDIRECTIONAL I/O LINES WITH TTL OR TTL/CMOS INTERFACE OPTION DIRECTIONAL I/O LINES WITH TTL OR OPEN-DRAIN INTERFACE OPTION COST RESISTOR OSCILLATOR OPTION NHIBIT OPTION INTERRUPTS : TIMER, SOFTWARE, AND EXTERNAL CALLABLE SELF-CHECK SUBROUTINES March 1989 1/31 EF6805U3 Figure 1 : EF6805U3 HMOS Microcomputer Block Diagram. ABSOLUTE MAXIMUM RATINGS Symbol V CC V in V in TA Supply Voltage Input Voltage (except TIMER in self-check mode and open-drain inputs) Input Voltage (open-drain pins, TIMER pin in self-check mode) Operating Temperature Range (T L to T H ) Storage Temperature Range Junction Temperature Plastic Package PLCC V Suffix T Suffix Parameter Value - 0.3 to + 7.0 - 0.3 to + 7.0 - 0.3 to + 15.0 0 to + 70 - 40 to + 85 - 40 to + 105 - 55 to + 150 150 150 Unit V V V C Tstg Tj C C This device contains circuitry to protect the inputs against damage due to high static voltages or electrical fields, however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V in and Vout be constrained to the range V SS (Vin or Vout) VCC. Reliability of operation is enhanced if unused inputs except EXTAL are tied to an appropriate logic voltage level (e.g., either V SS or VCC). THERMAL DATA J A Thermal Resistance Plastic PLCC 50 80 C/W 2/31 EF6805U3 POWER CONSIDERATIONS The average chip-junction temperature, TJ, in C can be obtained from : TJ = TA + (PD.JA) (1) Where : TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + PPORT PINT = ICC x VCC, Watts - Chip Internal Power PPORT = Port Power Dissipation, Watts - User Determined For most applications PPORT PINT and can be neglected. PPORT may become significant if the device is configured to drive Darlington bases or sink LED loads. An approximate relationship between PD and TJ (if PPORT is neglected) is : PD = K + (TJ + 273C) (2) Solving equations 1 and 2 for K gives : K = PD.(TA + 273C) + JA.PD2 (3) Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. ELECTRICAL CHARACTERISTICS(V CC = + 5.25Vdc 0.5Vdc, VS S = 0Vdc, T A = TL to TH unless otherwise noted) Symbol V IH Parameter Input High Voltage RESET (4.75 V CC 5.75) (V CC < 4.75) INT (4.75 V CC 5.75) (V CC < 4.75) All Other (except timer) Input High Voltage Timer Timer Mode Self-check Mode Input Low Voltage RESET INT All Other + - Min. 4.0 V CC - 0.5 4.0 V CC - 0.5 2.0 2.0 9.0 V SS V SS V SS 2.1 0.8 2 Typ. Max. V CC V CC V CC V CC V CC Unit V * * V IH V 10.0 V CC + 1.0 15.0 V * 0.8 1.5 0.8 V 4.0 2.0 4 V ac p -p V IL V IRE S V IRE S V IN T PD RESET Hystereris Voltages (see figures 10, 11 and 12) "Out of Reset" "Into Reset" INT Zero Crossing Input Voltage, Through a Capacitor Power Dissipation - (no port loading, VCC = 5.75V) T A = 0C T A = - 40C Input Capacitance EXTAL All Other Low Voltage Recover Low Voltage Inhibit Input Current TIMER (V i n = 0.4V) INT (V in = 2.4V to V CC ) EXTAL (V i n = 2.4V to V CC - crystal option) (V in = 0.4V - crystal option) RESET (V i n = 0.8V) - External Capacitor Charging Current mW 520 580 25 10 4.75 2.75 3.75 4.70 20 50 10 - 1600 - 40 V V A 20 740 800 pF C in VL V R VL V I I in - 40.0 * Due to internal biasing this input (when unused) floats to approximately 2.2V. 3/31 EF6805U3 SWITCHING CHARACTERISTICS (V C C = + 5.25Vdc 0.5Vdc, VS S = 0Vdc, T A = T L to TH unless otherwise noted) Symbol fo sc t c yc t WL , t WH t RWL f IN T Oscillator Frequency Cycle Time (4/f o s c ) INT, INT2, and TIMER Pulse Width (see interrupt section) RESET Pulse Width INT Zero-crossing Detection Input Frequency External Clock Input Duty Cycle (EXTAL) Crystal Oscillator Start-up Time* Parameter Min. 0.4 0.95 t c y c + 250 t c y c + 250 0.03 40 50 1 60 100 Typ. Max. 4.2 10 Unit MHz s ns ns kHz % ms PORT ELECTRICAL CHARACTERISTICS (V C C = + 5.25Vdc 0.5Vdc, VS S = 0Vdc, T A = T L to TH unless otherwise noted) PORT A WITH CMOS DRIVE ENABLED Symbol V OL V OH Output High Voltage I L o ad = - 100A I L o ad = - 10A Input High Voltage (I L o ad = - 300A max.) Input Low Voltage (I L o ad = - 500A max.) High Z State Input Current (V i n = 2.0V to V CC ) High Z State Input Current (V i n = 0.4V) Parameter Output Low Voltage (I L o ad = 1.6mA) 2.4 V CC - 1.0 2.0 V SS V CC 0.8 - 300 - 500 V V A A Min. Typ. Max. 0.4 Unit V V V IH V IL I IH I IL PORT B Symbol V OL Parameter Output Low Voltage I L o ad = 3.2mA I L o ad = 10mA (sink) Output High Voltage I L o ad = - 200A Darlington Current Drive (source) V O = 1.5V Input High Voltage Input Low Voltage High Z State Input Current 2.4 - 1.0 2.0 V SS <2 - 10 V CC 0.8 10 Min. Typ. Max. 0.4 1.0 V mA V V A Unit V V OH I OH V IH V IL I TS I PORT C AND PORT A WITH CMOS DRIVE DISABLED Symbol V OL V OH V IH V IL I TS I Parameter Output Low Voltage I L o ad = 1.6mA Output High Voltage I L o ad = - 100A Input High Voltage Input Low Voltage High Z State Input Current 2.4 2.0 V SS <2 V CC 0.8 10 Min. Typ. Max. 0.4 Unit V V V V s 4/31 EF6805U3 Figure 2 : TTL Equivalent Test Load (port B). Figure 3 : CMOS Equivalent Test Load (port A). Figure 4 : TTL Equivalent Test Load (port A andC). Figure 5 : Open-drain Equivalent Test Load (port C). SIGNAL DESCRIPTION The input and output signals for the MCU, shown in figure 1, are described in the following paragraphs. VCC AND VSS - Power is supplied to the MCU using these two pins. VCC is power and VSS is the ground connection. INT - This pin provides the capability for asynchronously applying an external interrupt to the MCU. Refer to Interrupts Section for additional information. XTAL AND EXTAL - These pins provide control input for theon-chip clock oscillator circuit. A crystal, a resistor, or an external signal, depending on user selectable manufacturing mask option, can be connected to these pins to provide a system clock with various degrees of stability/cost tradeoffs. Lead length and stray capacitance on these two pins should be minimized. Refer to Internal Clock Generator Options Section for recommendations about these inputs. NOTE : Pin 7 in DIL package/pin 8 in PLCC package is connected to internal protection. TIMER - The pin allows an external input to be used to control the internal timer circuitry and also to initiate the self test program. Refer to Timer Section for additional information about the timer circuitry. RESET - This pin allows resetting of the MCU at times other than the automatic resetting capability already in the MCU. The MCU can be reset by pulling RESET low. Refer to Resets Section for additional information. 5/31 EF6805U3 INPUT/OUTPUT LINES (PA0-PA7, PB0-PB7, PC0PC7, PD0-PD7) - These 32 liens are arranged into four 8-bit ports (A, B, C, and D). Ports A, B, and C are programmable as either inputs or outputs under software control of the data direction registers (DDRs). Port D is for digital input only and bit 6 may be used for a second interrupt INT2. Refer to Input/Output Section and Interrupts Section for additional information. MEMORY - The MCU is capable of addressing 4096 bytes of memory and I/O registers with its program counter. The EF6805U3 MCU has implemented 4090 of these bytes. This consists of : 3776 user ROM bytes, 192 self-check ROM bytes, 112 user RAM bytes, 7 port I/O bytes, 2 timer registers, and a miscellaneous register ; see figure 6 for the Address map. The user ROM has been split into two areas. The main user ROM area is from $080 to $F37. The last 8 user ROM locations at the bottom of memory are for the interrupt vectors. Figure 6 : EF6805U3 MCU Address Map. The MCU reserves the first-16 memory locations for I/O features, of which 10 have been implemented. These locations are used for the ports, the port DDRs, the timer and the INT2 miscellaneous register, and the 112 RAM bytes, 31 bytes are shared with the stack area. The stack must be used with care when data shares the stack area. The shared stack area is used during the processing of an interrupt or subroutine calls to save the contents of the CPU state. The register contents are pushed onto the stack in the order shown in figure 7. Since the stack pointer decrements during pushes, the low order byte (PCL) of the program counter is stacked first, then the high order four bits (PCH) are stacked. This ensures that the program counter is loaded correctly during pulls from the stack since the stack pointer increments when it pulls data from the stack. A subroutine call results in only the program counter (PCL, PCH) contents being pushed onto the stack ; the remaining CPU registers are not pushed. * Caution : Data direction registers (DDRs) are write only, they read as $FF. 6/31 EF6805U3 Figure 6 : Interrupt Stacking Order. Consequently, it can be treated as an independent central processor communicating with I/O and memory via internal address, data, and control buses. REGISTERS The 6805 Family CPU has five registers available to the programmer. They are shown in figure 8 and are explained in the following paragraphs. ACCUMULATOR (A) - The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manupulations. INDEX REGISTER (X) - The index register is an 8bit register used for the indexed addressing mode. It contains an 6-bit value that may be added to an instruction value to create an effective address. The index register can also be used for data manipulations using the read-modify-write instructions. The Index Register may also be used as a temporary storage area. CENTRAL PROCESSING UNIT The CPU of the EF6805 Family is implemented independently from the I/O or memory configuration. Figure 8 : Programming Model. PROGRAM COUNTER (PC) - The Program Counter is a 12 bit register that contains th address of the next instruction to be executed. STACK POINTER (SP) - The stack pointer is a 12bit register that contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $07F. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is then pulled from the stack. The seven most significant bits of the stack pointer are permanently set to 0000011. Subroutines and interrupts may be nested down to location $061 (31 bytes maximum) which allows the programmer to use up to 15 levels of subroutine calls (less if interrupts are allowed). CONDITION CODE REGISTER (CC) - The condition code register is a 5-bit register in which foour bits are used to indicate the results of the instruction just executed. These bits can be individually tested by a program and specific action taken as a result of their state. Each bit is explained in the following paragraphs. 7/31 EF6805U3 Half Carry (H) - Set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) - When this bit is set, the timer an external interrupts (INT and INT2) are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. Negative (N) - When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is a logical "1"). Zero (Z) - When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) - When set, this bit indicates that a carry or borrow ou of the Arithmetic Logic Unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions plus shifts and rotates. TIMER The timer circuitry for the EF6805U3 is shown in figure 10. The timer contains a single 8-bit software programmable counter with a 7-bit software selectable prescaler. The counter may be preset under program control and decrements toward zero. When the counter decrements to zero, the timer interrupt request bit, i.e., bit 7 of the timer control register (TCR), is set. Then if the timer interrupt is not masked, i.e.,bit 6 of the TCR and the I bit in the condition code register are both cleared, the processor receives an interrupt. After completion of the current instruction, the processor proceeds to store the appropriate registers on the stack, and then fetches the timer interrupt vector from locations $FF8 and $FF9 in order to begin servicing the interrupt. The counter continues to count after it reaches zero, allowing the software to determine the number of internal or external input clocks since the timer interrupt request bit was set. The counter may be read at any time by the processor without disturbing the count. The contents of the counter become stable prior to the read portion of a cycle and do not change during the read. The timer interrupt request bit remains set until cleared by the software. If a write occurs before the timer interrup is sericed, the interrupt is lost. TCR7 may also be used as a scanned status bit in a non-interrupt mode of operation (TCR6 = 1). The prescaler is a 7-bit divider which is used to extend the maximum length of the timer. Bit 0, bit 1, and bit 2 of the TCR are programmed to choose the appropriate prescaler outptu which is used as the counter input. The processor cannot writ eijto or read from the prescaler ; however, its contents are cleared to all zeros by the write operation into TCR when bit 3 of the written data equals one, which allows for truncation-free counting. The timer input can be configured for three different operating modes, plus a disable mode, depending on the value written to the TCR4 and TCR5 control bits. For further information see figure 9. Timer Input Mode 1 - If TCR5 adn TCR4 are both programmed to a zero, the inpt to the timer is from an internal clock and the external TIMER input is disabled. The internal clock mode canbe used for periodic interrupt generation, as well as a referene in frequency and event measurement. The internal clock is the instruction cycle clock. Timer Input Mode 2 - With TCR5 = 0 and TCR4 = 1, the internal clock and the TIMER input pin are ANDed to form the timer input signal. This mode can be used to measure external pulse widths. The external timer input pulse simply turns on the internal clock for the duration of the pulse widths. Timer Input Mode 3 - If TCR5 = 1 and TCR4 = 0, then all inputs to the timer are disabled. Timer Input Mode 4 - If TCR5 = 1 and TCR4 = 1, the internal clock input to the timer is disabled and the TIMER input pin becomes the input to the timer. The external TIMER pin can, in this mode, be used to count external events as well as external frequencies for generating periodic interrupts. TCR7 - Timer Interrupt Request Bit : 7 6 5 4 3 2 1 0 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0$009 * Write only (read as zero). 1 - Set when TDR goes to zero, or under program control 0 - Cleared on external Reset, Power-On-Reset, or under Program Control. TCR6 - Timer Interrupt Mask Bit : 1 - Timer Interrupt masked (disabled) Set on external Reset, Power-On-Reset, or under Program Control 0 - Cleared under Program Control. TCR5 - External or Internal Clock Source Bit : 1 - External Clock Source. Set on external Reset, Power-On-Reset, or under Program Control 0 - Cleared under Program Control. TCR4 - External Enable Bit : 1 - Enable external TIMER pin. Set on external Reset, Poxer-On-Reset, or under Program 8/31 EF6805U3 Control. 0 - Cleared under Program Control. TCR3 - Timer prescaler reset bit : A read of TCR3 TCR5 TCR4 0 0 1 1 0 1 0 1 Result Internal Clock to Timer AND of Internal Clock and TIMER Pin to Timer Input to timer disabled. TIMER Pin to Timer TCR2 , TCR1, and TCR0 - Prescaler address bits : 1 - All set on external Reset, Power-On-Reset or under Program Control. 0 - Cleared under Program Control. Figure 9 : Timer Control Register (TCR). TCR2 TCR1 TCR0 Result TCR2 TCR1 TCR0 Result always indicates a zero. 1 - Set on external Reset, Power-On-Reset or under Program Control. 0 - Cleared under Program Control Figure 10 : Timer Block Diagram. 0 0 0 0 0 0 1 1 0 1 0 1 + + + + 1 2 4 8 1 1 1 1 0 0 1 1 0 1 0 1 + 16 + 32 + 64 + 128 Notes : 1. Prescaler and 8-bit counter are clocked on the failing edge of the internal clock (AS) or external input. 2. Counter is written to during dat strobe (DS) and counts down continuously. SELF-CHECK - The self-check capability of the EF6805U3 MCU provides an internal check to determine if the part is functional. Connect the MCU as shown in figure 11 and monitor the output of Port C bit 3 for an oscillation of approximately 7Hz. A 10volt level (through a 10k resistor) on the timer input, pin 8 and pressing then releasing the RESET button, energizes the ROM-based self-check feature. The self-check program exercices the RAM, ROM, TIMER, interrupts, and I/O ports. Several of the self-check subroutines can be called by a user program with a JSR or BSR instruction. They are the RAM, ROM. The timer routine may also be called if the timer input is the internal 2 clock. To call those subroutines in customer application, please contact your local SGS-THOMSON Microelectronics sales office in order to obtain the complete description of the self-check program and the entrance/exit conditions. RAM SELF-CHECK SUBROUTINE - The RAM selfcheck is called at location $F84 and returns with the Z bit clear if any error is detected ; otherwise the Z bit is set. The RAM test causes each byte to count from 0 up to 0 again with a check after each count. The RAM test must be called with the stack pointer at $07F and A = 0. When run, the test checks every RAM cell except for $07F and $07E which are assumed to contain the return address. 9/31 EF6805U3 The A and X registers and all RAM locations except $07F and $07E are modified. ROM CHECKSUM SUBROUTINE - The ROM selfcheck is called at location $F95. The A register should be cleared before calling the routine. If any error is detected, it returns with the Z bit cleared ; Figure 11 : Self-check Connections. otherwise Z = 1, X = 0 on return, and A is zero if the test passes. RAM location $040 to $043 is overwritten. The checksum is the complement of the execution OR of the contents of the user ROM. * This connection depends on clock oscillator user selectable mask option. Use jumper if the RC mask option is selected. LED MEANINGS PC0 PC1 PC2 PC3 1 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 Remarks (1 : LED ON ; 0 : LED OFF) Bad I/O Bad Timer Bad RAM Bad ROM Bad Interrupts or Request Flag Good Device All Flashing 10/31 EF6805U3 TIMER SELF-CHECK SUBROUTINE - The timer self-check is called at location $F6D and returns with the Z bit cleared if any error was found ; otherwise Z = 1. In order to work correctly as a user subroutine, the internal 2 clock must be the clocking source and interrupts must be disabled. Also, on exit, the clock is running and the interrupt mask is not set so the caller must protect from interrupts if necessary. The A and X register contents are lost. This routine sets the prescaler for divide-by-128 and the timer data register is cleared. The X register is configured to count down the same as the timer data register. The two registers are then compared every 128 cycles until they both count down to zero. Any mismatch during the count down is considered as an error. The A and X registers are cleared on exit from the routine. Figure 12 : Typical Reset Schmitt Trigger Hysteresis. RESET The MCU can be reset three ways : by initial powerup, by the external reset input (RESET) and by an optional internal low-voltage detect circuit. The RESET input consists mainly of a Schmitt trigger which senses the RESET line logic level. A typical reset Schmitt trigger hysteresis curve is shown in figure 12. The Schmitt trigger provides an internal reset voltage if it senses a logical zero on the RESET pin. Power-On Reset (POR) - An internal reset is generated upon powerup that allows the internal clock generator to stabilize. A delay of t RHL milliseconds is required before allowing the RESET input to go high. Refer to the power and reset timing diagram of figure 13. Connecting a capacitor to the RESET input (as illustrated in figure 14) typically provides sufficient delay. During powerup, the Schmitt trigger switches on (removes reset) when RESET rises to VIRES+. Figure 13 : Power and Reset Timing. 11/31 EF6805U3 Figure 14 : RESET Configuration. External Reset Input - The MCU will be reset if a logical zero is applied to the RESET input for a period longer than one machine cycle (tcyc). Under this type of reset, the Schmitt trigger switches off at VIRES- to provide an internal reset voltage. Low-Voltage Inhibit (LVI) - The optional low-voltage detection circuit causes a reset of the MCU if the power supply voltage falls below a certain level (VLVI). The only requirement is that VCC remains at or below the VLVI threshold for one tcyc minimum. In typical applications, the VCC bus filter capacitor will eliminate negative-going voltage glitches of less than one tcyc. The output from the low-voltage detector is connected directly to the internal reset circuitry. It also forces the RESET pin low via a strong discharge device through a resistor. The internal reset will be removed once the power supply voltage rises above a recovery level (VLVR), at which time a normal power-on-reset occurs. INTERNAL CLOCK GENERATOR OPTIONS The internal clock generator circuit is designed to require a minimum of external components. A crystal, a resistor, a jumper wire, or an external signal may be used to generate a system clock with various stability/cost tradeoffs. The oscillator frequency is internally divided by four to produce the internal system clocks. A manufacturing mask option is used to select crystal or resistor operation. The different connection methods are shown in figure 15. Crystal specifications and suggested PC board layouts are given in figure 16. A resistor selection graph is given in figure 17. The crystal oscillator start-up time is a function of many variables : crystal parameters (especially RS), oscillator load capacitances, IC parameters, ambient temperature, and supply voltage. To ensure rapid oscillator start up, neither the crystal characteristics nor the load capacitances should exceed recommendations. When utilizing the on-board oscillator, the MCU should remain in a reset condition (reset pin voltage below VIRES+) until the oscillator has stabilized at its operating frequency. Several factors are involved in calculating the external reset capacitor required to satisfy this condition ; the oscillator start-up voltage, the oscillator stabilization time, the minimum VIRES+, and the reset charging current specification. Once VCC minimum is reached, the external RESET capacitor will begin to charge at a rate dependent on the capacitor value. The charging current is supplied from VCC through a large resistor, so it appears almost like a constant current source until the reset voltage rises above VIRES+. Therefore, the RESET pin will charge at approximately : (VIRES+).Cext = IRES.tRHL Assuming the external capacitor is initially discharged. 12/31 EF6805U3 Figure 15 : Clock Generator Options. Note : The recommended CL value with a 4.0 MHz crystal is 27pF, maximum, including system distributed capacitance. There is an internal capacitance of approximately 25pF on the XTAL pin. For crystal frequencies other than 4MHz, the total capacitance on each pin should be scaled as the inverse of the frquency ratio. For example, with a 2MHz crystal, use approximately 50pF on EXTAL and approximately 25pF on XTAL. The exact value depends on the Motional-Arm parameters of the crystal used. Figure 16 : Crystal Motional ARM parameters and Suggested PC Board layout. 13/31 EF6805U3 Figure 17 : Typical Frequency Selection for resistor (oscillator option). INTERRUPTS The microcomputers can be interrupted four different ways : through the external interrupt (INT) input pin, the internal timer interrupt request, the external port D bit 6 (INT2) input pin, or the software interrupt instruction (SWI). When any interrupt occurs : the current instruction (including SWI) is completed, processing is suspended, the present CPU state is pushed onto the stack, the interrupt bit (I) in the condition code register is set, the address of the interrupt routine is obtained from the appropriate interrupt vector address, and the interrupt routine is executed. Stacking the CPU register, setting the I bit, and vector fetching require a total of 11 tcyc periods for completion. A flowchart of the interrupt sequence is shown in figure 18. The interrupt service routine must end with a return from interrupt (RTI) instruction which allows the MCU to resume processing of the program prior to the interrupt (by unstacking the previous CPU state). Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction execution is complete. When the current instruction is complete, the processor checks all pending hardware interrupts and if unmasked, proceeds with interrupt processing ; otherwise the next instruction is fetched and executed. Note that masked interrupts are latched for later interrupt service. If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed as any other instruction. 14/31 EF6805U3 Figure 18 : RESET and interrupt Processing Flowchard. NOTE The timer and INT2 interrupts share the same vector address. The interrupt routine must determine the source by examining the interrupt request bits (TCR b7 and MR b7). Both TCR b7 and MR b7 can only be written to zero by software. The external interrupt, INT and INT2, are synchronized and then latched on the falling edge of the input signal. The INT2 interrupt has an interrupt request bit (bit 7) and a mask bit (bit 6) located in the miscellaneous register (MR). The INT2 interrupt is inhibited when the mask bit is set. The INT2 is always read as a digital input on port D. The INT2 and timer interrup requests bits, if set, cause the MCU to process an interrupt when the condition code I bit is clear. A sinuoidal input signal (fINT maximum) can be used to generate an external interrupt for use as a zerocrossing detector. This allows applications such as servicing time-of-day routines and engaging/disengaging ac power control devices. Off-chip full wave rectification provides an interrupt at every zero crossing of the ac signal and thereby provides a 2f clock. See figure 19. NOTE The INT (pin 3) is internally biased at approximately 2.2V due to the internal zero-crossing detection. 15/31 EF6805U3 A software interrupt (SWI) is an executable instruction which is executed regardless of the state of the I bit in the condition code register. SWIs are usually Figure 19 : Typical Interrupt Circuits. used as break-points for debugging or a system calls. INPUT/OUTPUT CIRCUITRY There are 32 input/output pins. The INT pin may be polled with branch instructions to provide an additional input pin. All pins on ports A, B, and C are programmable as either inputs or outputs under software control of the corresponding data direction register (DDR). See below I/O port control registers configuration. The port I/O programming is accomplished by writing the corresponding bit in the port DDR to a logic one for output or a logic zero for input. On reset all the DDRs are initialized to a logic zero state, placing the ports in the input mode. The port output registers are not initialized on reset and should be initialized by software before changing the DDRs from input to output. A read operation on a port programmed as an output will read the contents of the output latch regardless of the logic levels at the output pin, due to output loading. Refer to figure 20. PORT DATA REGISTER 7 Port A Addr = $000 Port B Addr = $001 Port C Addr = $002 Port D Addr = $003 0 PORT DATA DIRECTION REGISTER (DDR) 7 (1) Write only ; reads as all "1s" (2) 1 = Output.0 = input Cleared to 0 by Reset (3) Port A Addr = $004 Port B Addr = $005 Port C Addr = $006 0 16/31 EF6805U3 Figure 20 : Typical Port I/O Circuitry. Da t a Direction Registe r Bit 1 1 0 Lat ched Output Da t a Bit 0 1 X Output Sta te 0 1 High-Z** Input to M CU 0 1 Pin * DDR is a write-only register and reads as all "1s". ** Ports B and C are three-state ports. Port A has optional internal pull-up devices to provide CMOS data drive capability. See Electrical Characteristic tables for complete information. All input/output lines are TTL compatible as both inputs and outputs. Port A lines are CMOS compatible as outputs (mask option) while port B, C, and D lines are CMOS compatible as inputs. Port D lines are input only ; thus, there is no corresponding DDR. When programmed as outputs, port B is capable of sinking 10 milliamperes and sourcing 1 milliampere on each pin. The address map (figure 6) gives the addresses of data registers and data direction registers. Figure 21 provides some examples of port connections. CAUTION The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, $006). A read operation on these registers is undefined. Since BSET and BCLR are read-modify-write in function, they cannot be used to set or clear a single DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. The latched output data bit (see figure 20) must always be written. Therefore, any write to a port writes all of its data bits even though the port DDR is set to input. This may be used to initialize the data register and avoid undefined outputs ; however, care must be exercised when using read-modify-write instructions, since the data read corresponds to the pin level if the DDR is an input (zero) and corresponds to the latched output data when the DDR is an output (one). 17/31 EF6805U3 Figure 21 : Typical Port Connections. 18/31 EF6805U3 SOFTWARE BIT MANIPULATION The EF6805U3 MCU has the ability to set or clear any single random access memory or input/output bit (except the data direction register, see Caution below), with a single instruction (BSET, BCLR). Any bit in page zero including ROM, except the DDRs, can be tested, using the BRSET and BRCLR instructions, and the program branches as a result of its state. The carry bit equals the value of the bit referenced by BRSET or BRCLR. A rotate instruction may then be used to accumulate serial input data in a RAM location or register. The capability to work with any bit in RAM, ROM, or I/O allows the user to have individual flags in RAM or to handle I/O bits as control lines. The coding example in figure 21 illustrates the usefulness of the bit manipulation and test instructions. Figure 21 : Bit Manipulation Example. Assume that the MCU is to communicate with an external serial device. The external device has a data ready signal, a data output line, and a clock line to clock data one bit at a time. LSB first, out of the device. The MCU waits until the data is ready, clocks the external device, picks up the data in the carry flag (C bit), clears the clock line, and finally accumulates the data bit in a RAM location. Caution The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, and $006). A read operation on these registers is undefined. Since BSET and BCLR are readmodify-write functions, they cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. ADDRESSING MODES The EF6805P2 MCU has 10 addressing modes which are explained briefly in the following paragraphs. For additional details and graphical illustrations, refer to the 6805 Family User's Manual. The term "effective address" (EA) is used in describing the address modes. EA is defined as the address from which the argument for an instruction is fetched or stored. IMMEDIATE - In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants which do not change during program execution (e.g;, a constant used to initialize a loop counter). DIRECT - In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addresing al- lows the user to directly address the lowest 256 bytes in memory with a single 2-byte instruction. This includes the on-chip RAM and I/O registers and 128 bytes of ROM. Direct addressing is an effective use of both memory and time. EXTENDED - In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode. Instructions using extended addressing are capable of referencing arguments anywhere in memory with a single 3-byte instruction. When using the Motorola assembler, the programmer need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the shortest for of the instruction. RELATIVE - The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte following the opcode (the offset) is added to the PC if and only if the 19/31 EF6805U3 branch condition is true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from - 126 to + 129 from the opcode address. The programmer need not worry about calculating the correct offset when using the Motorola assembler since it calculates the proper offset and checks to see if it is within the span of the branch. INDEXED, NO OFFSET - In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. Thus, this addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. INDEXED, 8-BIT OFFSET - In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. This addressing mode is useful in selecting the kth element in an n element table. With this 2-byte instruction, k would typically be in X with the address of the beginning of the table in the instruction. As such, tables may begin anywhere within the first 256 addressable locations and could extend as far as location 510 ($1FE is the last location at which the instruction may begin). INDEXED, 16-BIT OFFSET - In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This addressing mode can be used in a manner similar to indexed, 8-bit offset, except that this 3-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. BIT SET/CLEAR - In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode, and the byte following the opcode specifies the direct address of the byte in which the specified bit is to be set or cleared. Thus, any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single 2-byte instruction. Caution The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, and $006). A read operation on these registers is undefined. Since BSET and BCLR are readmodify-write functions, they cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. BIT TEST AND BRANCH - The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit and condition (set or clear) which is to be tested is included in the opcode, and the address of the byte to be tested is in the single byte immediately following the opcode byte. The signed relative 8-bit offset is in the third byte and is added to the value of the PC if the branch condition is true. This single 3-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branching is from - 125 to + 130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. Caution The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, and $006). A read operation on these registers is undefined. Since BSET and BCLR are readmodify-write functions, they cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. INHERENT - In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as control instruction with no other arguments, are included in this mode. These instructions are one byte long. INSTRUCTION SET The EF6805U3 MCU has a set of 59 basic instructions, which when combined with the 10 addressing modes produce 207 usable opcodes. They can be divided into five different types : register/memory, read-modify-write, branch, bit manipulation, and control. The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. REGISTER/MEMORY INSTRUCTIONS - Most of these instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operands. Refer to table 1. READ-MODIFY-WRITE MODIFICATIONS - These instructions read a memory location or a register, 20/31 EF6805U3 modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is included in read-modify-write instructions through it does not perform the write. Rfer to table 2. Caution The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, and $006). A read operation on these registers is undefined. Since BSET and BCLR are readmodify-write functions, they cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. BRANCH INSTRUCTIONS - The branch instructions cause a branch from the program when a certain condition is met. Refer to table 3. BIT MANIPULATION INSTRUCTIONS - These instructions are used on any bit in the first 256 bytes of the memory. One group either sets or clears. The other group performs the bit test branch operations. Refer to table 4. Caution The corresponding DDRs for ports A, B, and C are write-only registers (registers at $004, $005, and $006). A read operation on these registers is undefined. Since BSET and BCLR are readmodify-write functions, they cannot be used to set or clear a DDR bit (all "unaffected" bits would be set). It is recommended that all DDR bits in a port be written using a single-store instruction. CONTROL INSTRUCTIONS - The control instructions control the MCU operations during program execution. Refer to table 5. ALPHABETICAL LISTING - The complete instruction set is given in alphabetical order in table 6. OPCODE MAP SUMMARY - Table 7 is an opcode map for the instructions used on the MCU. 21/31 EF6805U3 Table 1 : Register/Memory Instructions. 22/31 EF6805U3 Table 2 : Read-Modify-Write Instructions. 23/31 EF6805U3 Table 3 : Branch Instructions. Relative Addressing Mode Function Branch Always Branch Never Branch IFF Higher Branch IFF Lower or Same Branch IFF Carry Clear (branch IFF higher or same) Branch IFF Carry Set (branch IFF lower) Branch IFF Not Equal Branch IFF Equal Branch IFF Half Carry Clear Branch IFF Half Carry Set Branch IFF Plus Branch IFF Minus Branch IFF interrupt mask bit is clear. Branch IFF interrupt mask bit is set. Branch IFF interrupt line is low. Branch IFF interrupt line is high. Branch to Subroutine Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Op Code 20 21 22 23 24 24 25 25 26 27 28 29 2A 2B 2C 2D 2E 2F AD # Bytes 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 # Cycles 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 Table 4 : Bit Manipulation Instructions. Addressing Modes Bit Set/clear Function Mnemonic Op Code # Bytes # Cycles Bit Test and Branch Op Code 2*n 01 + 2 * n 10 + 2 * n 11 + 2 * n # Bytes 3 3 # Cycles 10 10 Branch IFF Bit n is set Branch IFF Bit n is clear Set Bit n Clear Bit n BRSET n (n = 0... 7) BRCLR n (n = 0... 7) BSET n (n = 0... 7) BCLR n (n = 0... 7) 2 2 7 7 24/31 EF6805U3 Table 5 : Control Instructions. Inherent Function Transfer A to X Transfer X to A Set Carry Bit Clear Carry Bit Set Interrupt Mask Bit Clear Interrupt Mask Bit Software Interrupt Return from Subroutine Return from Interrupt Reset Stack Pointer No-operation Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP Op Code 97 9F 99 98 9B 9A 83 81 80 9C 9D # Bytes 1 1 1 1 1 1 1 1 1 1 1 # Cycles 2 2 2 2 2 2 11 6 9 2 2 Table 6 : Instruction Set. Addressing Modes Indexed Indexed Bit Bit Test & Branch H I N Z C Conditi on Code Indexed Mnem Inherent Immediate Direct Extended Relative (no offset) (8 Bits) X X X X X X X X X X (16 Bits) Set/Clear X X X ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLL X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q q 0 25/31 EF6805U3 Table 6 : Instruction Set (continued). Addressing Modes Indexed Indexed Bit Bit Test & Branch H I N Z C Condition Code Mnem Inherent Immediate Direct Extended Relative Indexed (no offset) (8 Bits) (16 Bits) Set/clear CLI CLR CMP COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR NEQ NOP ORA ROL RSP RTI RTS SB C SE C SEI STA STX SUB SWI TAX TST TXA X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Z C Half Carry (from bit 3) ^ Test and Set if True, Cleared Otherwise Negative (sign bit) * Not Affected X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X q q q q q q q q q q q q q q q q q q q ? q q q q q q q q q q q 0 q q q q q q q q q q q q q q q q q q ? q q q 1 q q q 1 q q q q 0 q q 0 q q ? q q q q q q q 1 q q q q ? q q q q q q q q 1 q q q q q q q q q q ? q 1 q q q q q q q Condition Code Symbols : H I Interrupt Mask N 26/31 EF6805U3 HMOS 6805 FAMILY Features Technology Number of Pins On-chip RAM (bytes) On-chip User ROM (bytes) External Bus Bidirectional I/O Lines Unidirectional I/O Lines Other I/O Features External Interrupt Inputs STOP and WAIT EF6 805P2 HMOS 28 64 1100 None 20 None Timer 1 No EF680 5P6 HMOS 28 64 1796 None 20 None Timer 1 No E F680 5R2 HMOS 40 64 2048 None 24 6 Inputs Timer, A/D 2 No EF6 805R 3 HMOS 40 112 3776 None 24 6 Inputs Timer, A/D 2 No EF68 05U2 HMOS 40 64 2048 None 24 8 Inputs Timer 2 No EF 6805 U3 HMOS 40 112 3776 None 24 8 Inputs Timer 2 No 27/31 EF6805U3 Table 7 : 6805 HMOS Family Opcode MAP. 28/31 EF6805U3 PACKAGE MECHANICAL DATA 40 Pin Plastic Dual In Line Package (PDIP) Dim. A A1 B B1 C D D1 E E1 K1 K2 L e1 N mm inches Min Typ Max Min Typ Max 2.2 4.8 0.086 0.189 0.51 1.77 0.010 0.069 0.38 0.58 0.015 0.023 0.97 1.52 0.055 0.065 0.2 0.3 0.008 0.009 50.30 52.221.980 20.56 16.3 0.641 12.9 0.508 - - - - - - - - - - - - 3.18 4.44 1.25 0.174 2.54 0.10 Number of Pins 40 44 Pin Plastic Quad Package (PLCC) Dim. A A1 A3 B B1 D D1 D3 E E1 E3 K1 e N ND mm inches Min Typ Max Min Typ Max 4.2 5.08 0.165 0.200 0.64 0.020 2.29 3.30 0.090 0.130 0.331 0.661 17.40 17.650.685 0.695 16.51 16.660.650 0.656 12.70 0.500 17.40 17.650.685 0.695 16.51 16.660.650 0.656 12.70 0.500 1.27 0.050 Number of Pins 44 11 29/31 EF6805U3 ORDERING INFORMATION The information required when ordering a custom MCU is listed below. The ROM program may be transmitted to SGS-THOMSON on EPROM(s) or an EFDOS/MDOS* disk file. To initiate a ROM pattern for the MCU, it is necessary to first contact your local SGS-THOMSON representative or distributor. EPROMs One 2716 or 2732 type EPROMs, programmed with the customer program (positive logic sense for adSON will program on blank EPROM from the data file used to create the custom mask and aid in the verification process. ROM VERIFICATION UNITS (RVUs) Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units will have been made using the custom mask but are for the purpose of ROM verification only. For expediency they are usually unmarked, packaged in ceramic, and tested only at room temperature and 5 volts. These RVUs are included in the mask change and are not production parts. The RVUs are thus not guaranteed by SGS THOMSON. Quality Assurance, and should be discarded after verification is completed. FLEXIBLE DISKS The disk media submitted must be single-sided, EFDOS/MDOS* compatible floppies. The customer must write the binary file name and company name on the disk with a felt-tip-pen. The minimum EFDOS/MDOS* system files, as well as the absolute binary object file (Filename .LO type of file) from the 6805 cross assembler, must be on the disk. An object file made from a memory dump using the ROLLOUT command is also acceptable. Consider submitting a source listing as well as the following files : filename .LX (DEVICE/EXORciser loadable format) and filename .SA (ASCII Source Code). These files will of course be kept confidential and are used 1) to speed up the process in-house if any problems arise, and 2) to speed up the user-to-factory interface if the user finds any software errors and needs assistance quickly from SGS-THOMSON factory representatives. EFDOS is SGS-THOMSON Disk Operating System available on development systems such as DEVICE... MDOS* is MOTOROLA's Disk Operating System available on development systems such as EXORciser... * Requires prior factory approval. XXX = Customer ID) dress and data), may be submitted for pattern generation. After the EPROM is marked, it should be placed in conductive IC carriers and securely packed. Do not use styrofoam. VERIFICATION MEDIA All original pattern media (EPROMs or floppy disk) are filed for contractual purposes and are not returned. A computer listing of the ROM code will be generated and returned along with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed, and returned to SGS-THOMSON. The signed verification form constitutes the contractual agreement for creation of the customer mask. If desired, SGS-THOM- Whenever ordering a custom MCU is required, please contact your local SGS-THOMSON representative or SGS-THOMSON distributor and/or complete and send the attached "MCU customer ordering sheet" to your local SGS-THOMSON Microelectronics representative. 30/31 EF6805U3 ORDER CODES EF6805U3 Device Package P V Screen level Oper. temp. The table below horizontally shows all available suffix combinations for package, operating temperature and screening level. Other possibilities on request. Device C EF6805U3 Package J P E X FN X Oper. Temp. L* V T X X X Screening Level Std D G/B B/B X X Examples : EF6805U3P, EF6805U3FN, EF6805U3PV, EF6805U3FNV Package : C : Ceramic DIL, J : Cerdip DIL, P : Plastic DIL, E : LCCC, FN : PLCC Oper. temp. : L* : 0C to + 70C, V : - 40 C to + 85C, T : - 40C to + 105C, * : may be omitted. Screening level : Std : (no-end suffix), D : NFC 96883 level D, EXORciser is a registered trademark of MOTOROLA Inc. Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I 2 C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I 2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 31/31 |
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